IPR-PCIE/8 Altera, IPR-PCIE/8 Datasheet - Page 118

• Manufacturer Part Number: IPR-PCIE/8
• Description: IP CORE Renewal Of IP-PCIE/8
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCIE/8

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Express Compiler, x8 Link Width
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Signals
3–80
PCI Express Compiler User Guide
Figure 3–35. Global Reset Signals for x1 and x4 MegaCore Functions
The x1 and x4 MegaCore functions have three reset inputs, npor, srst,
and crst. npor is used internally for all sticky registers (registers that
may not be reset in L2 low power mode or by the fundamental reset).
npor is typically generated by a logical OR of the power-on-reset
generator and the perst signal as specified in the PCI Express card
electromechanical specification.
The srst signal is a synchronous reset of the data path state machines.
The crst signal is a synchronous reset of the nonsticky configuration
space registers. srst and crst should be asserted whenever the
l2_exit, hotrst_exit, or dlup_exit signals are asserted.
The reset block shown in
MegaCore function to provide some flexibility for implementation-
specific methods of generating a reset.
Figure 3–35
Figure 3–36. Global Reset Signals for x8 MegaCore Functions
PCI Express Compiler Version 6.1
shows the function’s global reset signals.
Other Power
On Reset
Other Power
On Reset
perst#
Figure 3–36
perst#
is not included as part of the
x1 or x4 MegaCore
npor
PCI Express
srst
crst
l2_exit
hotrst_exit
dlup_exit
Function
x8 MegaCore
npor
PCI Express
rstn
l2_exit
hotrst_exit
dlup_exit
Function
Altera Corporation
December 2006