EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 105

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
October 2007
Following the Two-Multiplier Adder units are the pipeline registers, the
second-stage adders, and an output register stage. You can configure the
second-stage adders to provide the following alternative functions per
Half-Block:
Equation 5–2. Four-Multiplier Adder Equation
Equation 5–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
In these equations, n denotes sample time, and P[36..0] are the results
from the Two-Multiplier Adder units.
Equation 5–2
operations (Four-Multiplier Adder), and
18-bit × 18-bit multiplication operation but with maximum of a 44-bit
accumulation capability by feeding the output of the unit back to itself.
This is shown in
You can bypass all register stages depending on which mode you select.
provides a sum of four 18-bit × 18-bit multiplication
Figure
W
Z[37..0] = P
n
[43..0] = W
5–3.
0
n-1
[36..0] + P
[43..0] ± Z
Stratix III Device Handbook, Volume 1
Equation 5–3
DSP Blocks in Stratix III Devices
1
[36..0]
n
[37..0]
provides a four
5–5