EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 177

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–18. External Clock Outputs for Top/Bottom PLLs
Notes to
(1)
(2)
(3)
Altera Corporation
November 2007
These clock output pins can be fed by any one of the C[9..0], m counters.
The CLKOUT0p and CLKOUT0n pins can be either single-ended or differential clock outputs. CLKOUT1 and CLKOUT2
pins are dual-purpose I/O pins that can be used as two single-ended outputs or one differential external feedback
input pin. CLKOUT3 and CLKOUT4 pins are two single-ended output pins.
These external clock enable signals are available only when using the altclkctrl megafunction.
Top/Bottom
PLLs
Figure
PLL_<#>_CLKOUT0p (1), (2)
6–18:
clkena0 (3)
clkena1 (3)
m(fbout)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
PLL_<#>_CLKOUT0n (1), (2)
Any of the output counters (C[9..0] on Top/Bottom PLLs and
C[6..0] on Left/Right PLLs) or the M counter can feed the dedicated
external clock outputs, as shown in
counter or frequency can drive all output pins available from a given PLL.
Each Left/Right PLL supports two clock I/O pins, configured as either
two single-ended I/Os or one differential I/O pair. When using both pins
as single-ended I/Os, one of them can be the clock output while the other
pin is the external feedback input (FB) pin. Hence, Left/Right PLLs only
support external feedback mode for single-ended I/O standards only.
PLL_<#>_FBp/CLKOUT1 (1), (2)
clkena3 (3)
clkena2 (3)
PLL_<#>_FBn/CLKOUT2 (1), (2)
Clock Networks and PLLs in Stratix III Devices
Figures 6–18
Stratix III Device Handbook, Volume 1
clkena4 (3)
clkena5 (3)
PLL_<#>_CLKOUT3
and 6–19. Therefore, one
(1), (2)
PLL_<#>_CLKOUT4
(1), (2)
Internal Logic
6–27