EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 387

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 11–10. Multi-Device Fast AS Configuration When devices Receive the Same Data
Note to
(1)
Altera Corporation
November 2007
Connect the pull-up resistors to a 3.3-V supply.
Figure
Serial Configuration
11–10:
Device
DATA
DCLK
ASDI
nCS
V
CC
10 kΩ
(1)
Estimating Active Serial Configuration Time
Active serial configuration time is dominated by the time it takes to
transfer data from the serial configuration device to the Stratix III device.
This serial interface is clocked by the Stratix III DCLK output (generated
from an internal oscillator). As the Stratix III device only supports fast AS
configuration, the DCLK frequency needs to be set to 40 MHz (25 ns).
Therefore, the minimum configuration time estimate for an EP3SL50
device (15 MBits of uncompressed data) is:
RBF Size × (minimum DCLK period / 1 bit per DCLK cycle) = estimated
minimum configuration time
15 Mbits × (25 ns / 1 bit) = 375 ms
V
CC
10 kΩ
(1)
GND
V
CC
10 kΩ
(1)
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCSO
ASDO
FPGA Master
Stratix III
MSEL2
MSEL1
MSEL0
nCEO
V
CCPGM
GND
Stratix III Device Handbook, Volume 1
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
Configuring Stratix III Devices
FPGA Slave
FPGA Slave
FPGA Slave
Stratix III
Stratix III
Stratix III
MSEL2
MSEL1
MSEL0
MSEL2
MSEL1
MSEL0
MSEL2
MSEL1
MSEL0
nCEO
nCEO
nCEO
GND
GND
GND
N.C.
N.C.
N.C.
V
V
V
CCPGM
CCPGM
CCPGM
11–27