EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 403

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

JTAG
Configuration
Altera Corporation
November 2007
f
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on PCBs with tight lead spacing. The BST architecture
can test pin connections without using physical test probes and capture
functional data while a device is operating normally. You can also use the
JTAG circuitry to shift configuration data into the device. The Quartus II
software automatically generates SOFs that can be used for JTAG
configuration with a download cable in the Quartus II software
programmer.
For more information on JTAG boundary-scan testing and commands
available using Stratix III devices, refer to the following documents:
■
■
Stratix III devices are designed such that JTAG instructions have
precedence over any device configuration modes. Therefore, JTAG
configuration can take place without waiting for other configuration
modes to complete. For example, if you attempt JTAG configuration of
Stratix III devices during PS configuration, PS configuration is terminated
and JTAG configuration begins.
1
1
All user I/O pins are tri-stated during JTAG configuration.
explains each JTAG pin's function.
IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Device
of the Stratix III Device Handbook
Jam Programming and Testing Language Specification
You cannot use the Stratix III decompression or design security
features if you are configuring your Stratix III device when
using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI,
TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has
an internal weak pull-down resistor, while the TDI, TMS, and
TRST pins have weak internal pull-up resistors (typically
25 kΩ). JTAG output pin TDO and all JTAG input pins are
powered by the 2.5 V/3.0 V/3.3 V V
support only LVTTL I/O standard.
Stratix III Device Handbook, Volume 1
Configuring Stratix III Devices
CCPD
. All the JTAG pins
Table 11–11
chapter
11–43