EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 410

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Device Configuration Pins
Device
Configuration
Pins
11–50
Stratix III Device Handbook, Volume 1
Table 11–13. Stratix III Configuration Pin Summary
DATA[7..1]
CRC_ERROR
INIT_DONE
CONF_DONE
Description
nSTATUS
nCONFIG
CLKUSR
PORSEL
DATA0
TRST
TDI
TMS
TCK
TDO
nCE
f
Jam STAPL
Jam STAPL, JEDEC standard JESD-71, is a standard file format for
in-system programmability (ISP) purposes. Jam STAPL supports
programming or configuration of programmable devices and testing of
electronic systems, using the IEEE 1149.1 JTAG interface. Jam STAPL is a
freely licensed open standard.
The Jam Player provides an interface for manipulating the IEEE Std.
1149.1 JTAG TAP state machine.
For more information on JTAG and Jam STAPL in embedded
environments, refer to
Embedded
at www.altera.com.
The following tables describe the connections and functionality of all the
configuration-related pins on the Stratix III devices.
summarizes the Stratix III configuration pins and their power supply.
Input/Output
Bidirectional
Bidirectional
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Processor. To download the jam player, visit the Altera web site
Dedicated
Note (1)
AN 122: Using Jam STAPL for ISP and ICR via an
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
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(Part 1 of 2)
V
V
V
Powered By
CCPGM
CCPGM
CCPGM
V
V
V
Pull-up
Pull-up
Pull-up
Pull-up
V
V
V
V
V
CCPGM
CCPGM
CCPGM
CCPD
CCPD
CCPD
CCPD
CCPD
/V
/V
/V
CCIO
CCIO
CCIO
Table 11–13
Configuration Mode
Optional, all modes
Optional, all modes
All modes except
Altera Corporation
All modes
All modes
All modes
All modes
All modes
November 2007
Optional
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG
FPP