EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 164

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clock Networks in Stratix III Devices
6–14
Stratix III Device Handbook, Volume 1
GCLK7
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
GCLK13
GCLK14
GCLK15
RCLK[0..11]
RCLK[12..31]
RCLK[32..43]
RCLK[44..63]
RCLK[64..69]
RCLK[70..75]
RCLK[76..81]
RCLK[82..87]
Table 6–8. Stratix III PLL Connectivity to GCLKs (Part 2 of 2)
Table 6–9. Stratix III Regional clock Outputs From PLLs
Clock Resource
Clock Network
L1
v
—
—
—
—
—
—
—
L1
—
—
—
—
—
—
—
—
—
Table 6–9
Clock Source Control for PLLs
The clock input to Stratix III PLLs comes from clock input multiplexers.
The clock multiplexer inputs come from dedicated clock input pins, PLLs
through the GCLK and RCLK networks, or from dedicated connections
between adjacent Top/Bottom and Left/Right PLLs. The clock input
sources to Top/Bottom and Left/Right PLLs (L2, L3, T1, T2, B1, B2, R2,
and R3) are shown in
to Left/Right PLLs (L1, L4, R1, and R4) are shown in
L2
v
—
—
—
—
—
—
—
L2
—
—
—
—
—
—
—
—
—
L3
v
—
—
—
—
—
—
—
L3
—
—
—
—
—
—
—
—
—
shows how the PLL clock outputs connect to RCLK networks.
L4
v
—
—
—
—
—
—
—
L4
—
—
—
—
—
—
—
—
—
B1
B1
v
v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Figure
PLL Number
PLL Number
B2
v
—
—
—
—
—
—
—
—
B2
v
—
—
—
—
—
—
—
6–9; the corresponding clock input sources
R1
—
v
v
v
v
—
—
—
—
R1
—
—
—
—
—
—
v
—
R2
v
v
v
v
—
—
—
—
—
R2
—
—
v
—
—
—
—
—
R3
v
v
v
v
—
—
—
—
—
R3
v
—
—
—
—
—
—
—
R4
—
v
v
v
v
—
—
—
—
Figure
R4
—
—
—
—
—
v
—
—
Altera Corporation
November 2007
T1
v
v
v
v
—
—
—
—
—
6–10.
T1
v
—
—
—
—
—
—
—
T2
v
—
—
—
—
—
v
v
v
T2
v
—
—
—
—
—
—
—