EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 298

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
8–28
Stratix III Device Handbook, Volume 1
Figure 8–12
reference clock goes into the DLL to a chain of up to 16 delay elements.
The phase comparator compares the signal coming out of the end of the
delay chain block to the input reference clock. The phase comparator then
issues the upndn signal to the Gray-code counter. This signal increments
or decrements a six-bit delay setting (DQS delay settings) that will
increase or decrease the delay through the delay element chain to bring
the input reference clock and the signals coming out of the delay element
chain in phase.
DLL1
DLL2
DLL3
DLL4
Table 8–11. DLL Reference Clock Input for EP3SL200, EP3SE260
and EP3SL340 Devices
DLL
(Top/Bottom)
CLK12P,
CLK13P,
CLK14P,
CLK15P
CLK12P,
CLK13P,
CLK14P,
CLK15P
shows a simple block diagram of the DLL. The input
CLK4P,
CLK5P,
CLK6P,
CLK4P,
CLK5P,
CLK6P,
CLK7P
CLK7P
CLKIN
(Left/Right)
CLK10P,
CLK10P,
CLK11P
CLK11P
CLK0P,
CLK1P,
CLK2P,
CLK0P,
CLK1P,
CLK2P,
CLK8P,
CLK9P,
CLK8P,
CLK9P,
CLK3P
CLK3P
CLKIN
(Top/Bottom)
PLL_B1
PLL_B2
PLL_T1
PLL_T2
PLL
(Left/Right)
PLL_R3
PLL_R4
PLL_R1
PLL_R2
PLL_L1
PLL_L2
PLL_L3
PLL_L4
Altera Corporation
PLL
November 2007