EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 50

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Adaptive Logic Modules
2–16
Stratix III Device Handbook, Volume 1
add/subtract control signals. These control signals are good candidates
for the inputs that are shared between the four LUTs in the ALM. The
synchronous clear and synchronous load options are LAB-wide signals
that affect all registers in the LAB. These signals can also be individually
disabled or enabled per register. The Quartus II software automatically
places any registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. The two-bit carry select
feature in Stratix III devices halves the propagation delay of carry chains
within the ALM. Carry chains can begin in either the first ALM or the fifth
ALM in an LAB. The final carry-out signal is routed to a ALM, where it is
fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 20 (10 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together
automatically. For enhanced fitting, a long carry chain runs vertically
allowing fast horizontal connections to TriMatrix™ memory and DSP
blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high
fan-in arithmetic function is implemented, the LAB can support carry
chains that only utilize either the top half or the bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs
in the LAB available for implementing narrower fan-in functions in
normal mode. Carry chains that use the top five ALMs in the first LAB
carry into the top half of the ALMs in the next LAB within the column.
Carry chains that use the bottom five ALMs in the first LAB carry into the
bottom half of the ALMs in the next LAB within the column. In every
alternate LAB column, the top half can be bypassed; in the other MLAB
columns, the bottom half can be bypassed.
1
Refer to
information on carry chain interconnect.
“ALM Interconnects” on page 2–22
for more
Altera Corporation
October 2007