EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 296

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
8–26
Stratix III Device Handbook, Volume 1
1
DLL1
DLL2
DLL3
DLL4
DLL1
DLL2
Table 8–8. DLL Reference Clock Input for EP3SE50, EP3SL50 and EP3SL70
Devices
Table 8–9. DLL Reference Clock Input for EP3SE80, EP3SE110, and
EP3SL150 Devices in the 780-pin Package
DLL
DLL
When you have a dedicated PLL that only generate the DLL
input reference clock, set the PLL mode to No Compensation, or
the Quartus II software will change it automatically. Because the
PLL does not use any other outputs, it does not need to
compensate for any clock paths.
(Top/Bottom)
CLK12P,
CLK13P,
CLK14P,
CLK12P,
CLK13P,
CLK14P,
CLK15P
CLK15P
CLK4P,
CLK5P,
CLK6P,
CLK4P,
CLK5P,
CLK6P,
CLK7P
CLK7P
CLKIN
(Top/Bottom)
CLK12P,
CLK13P,
CLK14P,
CLK15P
CLK4P,
CLK5P,
CLK6P,
CLK7P
CLKIN
(Left/Right)
(Left/Right)
CLK10P,
CLK10P,
CLK11P
CLK11P
CLK0P,
CLK1P,
CLK2P,
CLK0P,
CLK1P,
CLK2P,
CLK8P,
CLK9P,
CLK8P,
CLK9P,
CLK3P
CLK3P
CLKIN
CLK0P,
CLK1P,
CLK2P,
CLK0P,
CLK1P,
CLK2P,
CLK3P
CLK3P
CLKIN
(Top/Bottom)
(Top/Bottom)
PLL_T1
PLL_B1
PLL_T1
PLL_B1
PLL_B1
PLL_T1
PLL
PLL
Altera Corporation
November 2007
(Left/Right)
(Left/Right)
PLL_R2
PLL_R2
PLL_L2
PLL_L2
PLL_L2
PLL
N/A
PLL