EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 754

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–242
Stratix III Device Handbook, Volume 2
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
3.3-V
LVCMOS
3.0-V LVTTL
I/O Standard
Table 1–104. EP3SL340 Row Pin Delay Adders for Regional Clock
Table 1–105. EP3SE50 Column Pins Input Timing Parameters (Part 1 of 4)
Parameter
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
Industrial Commercial V
Parameter
—
—
—
—
Table 1–104
Regional Clock.
EP3SE50 I/O Timing Parameters
Table 1–105
parameters for EP3SE50 devices for single-ended I/O standards.
Table 1–105
single-ended I/O standards.
t
t
t
t
t
t
t
t
t
t
t
t
SU
SU
SU
SU
SU
SU
H
H
H
H
H
H
Fast Model
Industrial Commercial
-0.075
-0.066
1.75
1.77
—
—
—
—
—
—
—
—
—
—
—
—
specifies EP3SE50 Column Pins Input Timing parameters for
specifies EP3SL340 Row Pin delay adders when using the
through
Fast Model
Table 1–108
CCL
-0.729
-0.304
-0.729
-0.304
-0.729
-0.304
0.837
0.412
0.837
0.412
0.837
0.412
—
—
—
—
-2
=1.1V V
CCL
-1.055 -1.144 -1.238 -1.187 -1.479
-0.643 -0.767 -0.876 -0.826 -0.714
-1.055 -1.144 -1.238 -1.187 -1.479
-0.643 -0.767 -0.876 -0.826 -0.714
-1.055 -1.144 -1.238 -1.187 -1.479
-0.643 -0.767 -0.876 -0.826 -0.714
show the maximum I/O timing
V
1.197
0.785
1.197
0.785
1.197
0.785
1.1V
2.939
0.039
0.062
2.94
CCL
-2
-3
=1.1V V
=
V
1.305
0.928
1.305
0.928
1.305
0.928
1.1V
CCL
-3
CCL
=
3.277
3.216
0.101
0.113
-4
=1.1V V
V
1.413
1.051
1.413
1.051
1.413
1.051
1.1V
CCL
-4
=
CCL
Altera Corporation
V
1.354
0.993
1.354
0.993
1.354
0.993
1.1V
3.131
3.062
0.053
0.102
CCL
=1.1V V
November 2007
=
-4L
-4L
V
1.640
0.875
1.640
0.875
1.640
0.875
0.9V
CCL
CCL
=
2.881
2.916
0.358
0.526
=0.9V
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns