EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 210

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–60
Stratix III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Table 6–20. PLL Counter Settings
LSB
(2)
X
0
Most significant bit (MSB)
Least significant bit (LSB).
Counter-bypass bit.
Table
X
X
6–20:
X
X
X
X
Bypassing PLL
Bypassing a PLL counter results in a multiply (m counter) or a divide (n
and C0 to C9 counters) factor of one.
Table 6–20
PLLs.
1
Dynamic Phase-Shifting
The dynamic phase-shifting feature allows the output phases of
individual PLL outputs to be dynamically adjusted relative to each other
and to the reference clock without the need to send serial data through the
scan chain of the corresponding PLL. This feature simplifies the interface
and allows you to quickly adjust clock-to-out (t
Table 6–19. loop_filter_c Bit Settings
X
X
PLL Scan Chain Bits [0..10] Settings
X
X
LFC[1]
To bypass any of the PLL counters, set the bypass bit to 1. The
values on the other bits is ignored. To bypass the VCO post-scale
counter (K), set the corresponding bit to 0.
shows the settings for bypassing the counters in Stratix III
0
0
1
X
X
X
X
X
X
LFC[0]
X
X
0
1
1
MSB
1
0
(1)
(3)
(3)
PLL counter bypassed
PLL counter not bypassed
because bit 10 (
set to 0
CO
) delays by changing
Decimal Value for
Description
Altera Corporation
Setting
November 2007
0
1
3
MSB
) is