EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 383

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
The serial clock (DCLK) generated by the Stratix III device controls the
entire configuration cycle and provides the timing for the serial interface.
Stratix III devices use an internal oscillator to generate DCLK. Using the
MSEL[] pins, you can select to use a 40 MHz oscillator.
In fast AS configuration schemes, Stratix III devices drive out control
signals on the falling edge of DCLK. The serial configuration device
responds to the instructions by driving out configuration data on the
falling edge of DCLK. Then the data is latched into the Stratix III device on
the following falling edge of DCLK.
In configuration mode, Stratix III devices enable the serial configuration
device by driving the nCSO output pin low, which connects to the chip
select (nCS) pin of the configuration device. The Stratix III device uses the
serial clock (DCLK) and serial data output (ASDO) pins to send operation
commands and/or read address signals to the serial configuration
device. The configuration device provides data on its serial data output
(DATA) pin, which connects to the DATA0 input of the Stratix III devices.
After all configuration bits are received by the Stratix III device, it releases
the open-drain CONF_DONE pin, which is pulled high by an external
10-kΩ resistor. Initialization begins only after the CONF_DONE signal
reaches a logic high level. All AS configuration pins (DATA0, DCLK, nCSO,
and ASDO) have weak internal pull-up resistors that are always active.
After configuration, these pins are set as input tri-stated and are driven
high by the weak internal pull-up resistors. The CONF_DONE pin must
have an external 10-kΩ pull-up resistor in order for the device to
initialize.
In Stratix III devices, the initialization clock source is either the 10 MHz
(typical) internal oscillator (separate from the active serial internal
oscillator) or the optional CLKUSR pin. By default, the internal oscillator
is the clock source for initialization. If you use the internal oscillator, the
Stratix III device provides itself with enough clock cycles for proper
initialization. You also have the flexibility to synchronize initialization of
multiple devices or to delay initialization with the CLKUSR option. You
can turn on the Enable user-supplied start-up clock (CLKUSR) option in
the Quartus II software from the General tab of the Device and Pin
Options dialog box. When you enable the user supplied start-up clock
option, the CLKUSR pin is the initialization clock source. Supplying a
clock on CLKUSR will not affect the configuration process. After all
configuration data has been accepted and CONF_DONE goes high,
CLKUSR is enabled after 600 ns. After this time period elapses, Stratix III
devices require 4,436 clock cycles to initialize properly and enter user
mode. Stratix III devices support a CLKUSR f
Stratix III Device Handbook, Volume 1
Configuring Stratix III Devices
MAX
of 100 MHz.
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