EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 299

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 8–12. Simplified Diagram of the DQS Phase Shift Circuitry
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
November 2007
Input Reference
All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY megafunction in the Quartus II
software.
The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin.
Refer to
Phase offset settings can only go to the DQS logic blocks.
DQS delay settings can go to the logic array, the DQS logic block, and the leveling circuitry.
Clock (2)
Figure
Tables 8–8
8–12:
DLL
through
Comparator
Phase
The DLL can be reset from either the logic array or a user I/O pin. Each
time the DLL is reset, you must wait for 1280 clock cycles before you can
capture the data properly.
The DLL can shift the incoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°,
67.5°, 72°, 90°, 108°, 120°, 135°, 144°, or 180°, depending on the DLL
frequency mode. The shifted DQS signal is then used as the clock for the
DQ IOE input registers.
All DQS and CQn pins, referenced to the same DLL, can have their input
signal phase shifted by a different degree amount but all must be
referenced at one particular frequency. For example, you can have a 90°
phase shift on DQS1T and a 60° phase shift on DQS2T, referenced from a
200-MHz clock. Not all phase-shift combinations are supported,
8–11
for exact PLL and input clock pin.
Delay Chains
clock enable
upndn
Up/Down
Counter
6
External Memory Interfaces in Stratix III Devices
6
addnsub_a
addnsub_b
6
Phase offset settings
from the logic array
Phase offset settings
from the logic array
6
Note (1)
6
Stratix III Device Handbook, Volume 1
DQS Delay
Settings (4)
Control
Control
Phase
Phase
Offset
Offset
6
6
Phase offset
settings to DQS pin
on left or right edge (3)
Phase offset
settings to DQS pins
on top or bottom edge (3)
8–29