EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 293

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
The DQS phase-shift circuitry is connected to the DQS logic blocks that
control each DQS or CQn pin. The DQS logic blocks allow the DQS delay
settings to be updated concurrently at every DQS or CQn pin.
DLL
The DQS phase-shift circuitry uses a DLL to dynamically measure the
clock period needed by the DQS/CQn pin. The DLL, in turn, uses a
frequency reference to dynamically generate control signals for the delay
chains in each of the DQS and CQn pins, allowing it to compensate for
PVT variations. The DQS delay settings are Gray-coded to reduce jitter
when the DLL updates the settings. The phase-shift circuitry needs a
maximum of 1280 clock cycles to calculate the correct input clock period.
Data should not be sent during these clock cycles since there is no
guarantee it will be properly captured. As the settings from the DLL may
not be stable until this lock period has elapsed, you should be aware that
anything using these settings (including the leveling delay system) may
be unstable during this period.
1
There are four DLLs in a Stratix III device, located in each corner of the
device. These four DLLs can support a maximum of four unique
frequencies, with each DLL running at one frequency. Each DLL can have
two outputs with different phase offsets, which allow one Stratix III
device to have eight different DLL phase shift settings.
the DLL and I/O bank locations in Stratix III devices, from a
package-bottom view.
You can still use the DQS phase-shift circuitry for any memory
interfaces that are less than 100 MHz. The DQS signal will be
shifted by 2.5 ns. Even if the DQS signal is not shifted exactly to
the middle of the DQ valid window, the I/O element should still
be able to capture the data in low frequency applications where
a large amount of timing margin is available.
External Memory Interfaces in Stratix III Devices
Stratix III Device Handbook, Volume 1
Figure 8–11
shows
8–23