EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 329

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential I/O
Termination
Altera Corporation
November 2007
With pre-emphasis, the output current is boosted momentarily during
switching to increase the output slew rate. The overshoot introduced by
the extra current happens only during switching and does not ring,
unlike the overshoot caused by signal reflection. The amount of
pre-emphasis needed depends on the attenuation of the high-frequency
component along the transmission line.
Stratix III pre-emphasis is programmable to create the right amount of
overshoot at different transmission conditions. There are four settings for
pre-emphasis: zero, low, medium, and high. The default setting is low.
For a particular design, simulation with an LVDS buffer and transmission
line can be used to determine the best pre-emphasis setting. The VOD is
also programmable with four settings: low, medium low, medium high,
and high. The default setting is medium low.
option on each differential receiver channel for LVDS standards. On-chip
termination saves board space by eliminating the need to add external
resistors on the board. You can enable on-chip termination in the
Quartus II software Assignment editor.
SERDES block clock pins: CLK (0, 2, 9, and 11). It is not supported
for column I/O pins, high speed clock pins CLK [1, 3, 8, 10], or the
corner PLL clock inputs.
Figure 9–11
Figure 9–11. On-Chip Differential I/O Termination
Stratix III devices provide a 100-Ω, on-chip differential termination
On-chip differential termination is supported on all row I/O pins and
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
illustrates device on-chip termination.
Transmitter
LVDS
Z
Z
0
0
= 50 Ω
= 50 Ω
Stratix III Device Handbook, Volume 1
Receiver with On-Chip
Stratix III Differential
100 Ω Termination
R
D
9–13