EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 182

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–32
Stratix III Device Handbook, Volume 1
Clock Feedback Modes
Stratix III PLLs support up to six different clock feedback modes. Each
mode allows clock multiplication and division, phase shifting, and
programmable duty cycle.
supported by Stratix III device PLLs.
1
Source Synchronous Mode
If data and clock arrive at the same time on the input pins, the same phase
relationship is maintained at the clock and data ports of any IOE input
register.
this mode. This mode is recommended for source-synchronous data
transfers. Data and clock signals at the IOE experience similar buffer
delays as long as you use the same I/O standard.
Note to
(1)
Source-synchronous mode
No-compensation mode
Normal mode
Zero-delay buffer (ZDB) mode
External-feedback mode
LVDS compensation
Table 6–14. Clock Feedback Mode Availability
External feedback mode supported for single-ended inputs and outputs only on
Left/Right PLLs.
Clock Feedback Mode
Table
Figure 6–21
The input and output delays are fully compensated by a PLL
only when using the dedicated clock input pins associated with
a given PLL as the clock sources. For example, when using
PLL_T1 in normal mode, the clock delays from the input pin to
the PLL clock output-to-destination register are fully
compensated provided the clock input pin is one of the
following four pins: CLK12, CLK13, CLK14, or CLK15. When an
RCLK or GCLK network drives the PLL, the input and output
delays may not be fully compensated in the Quartus II software.
6–14:
shows an example waveform of the clock and data in
Table 6–14
Top/Bottom PLLs
shows the clock feedback modes
Yes
Yes
Yes
Yes
Yes
No
Availability
Altera Corporation
Left/Right PLLs
November 2007
Yes
Yes
Yes
Yes
Yes
Yes
(1)