EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 200

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
6–50
Stratix III Device Handbook, Volume 1
Phase-Shift Implementation
Phase shift is used to implement a robust solution for clock delays in
Stratix III devices. Phase shift is implemented by using a combination of
the VCO phase output and the counter starting time. The VCO phase
output and counter starting time is the most accurate method of inserting
delays, since it is purely based on counter settings, which are
independent of process, voltage, and temperature.
You can phase-shift the output clocks from the Stratix III PLLs in either of
these two resolutions:
■
■
Fine-resolution phase shifts are implemented by allowing any of the
output counters (C[n..0]) or the m counter to use any of the eight
phases of the VCO as the reference clock. This allows you to adjust the
delay time with a fine resolution. The minimum delay time that you can
insert using this method is defined by:
where f
For example, if f
and Φfine equals 156.25 ps. This phase shift is defined by the PLL
operating frequency, which is governed by the reference clock frequency
and the counter settings.
Coarse-resolution phase shifts are implemented by delaying the start of
the counters for a predetermined number of counter clocks. You can
express coarse phase shift as:
where C is the count value set for the counter delay time, (this is the initial
setting in the PLL usage section of the compilation report in the
Quartus II software). If the initial value is 1, C – 1 = 0° phase shift.
Φ
Φ
fine
coarse
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
=
=
REF
1
8
C − 1
T
is the input reference clock frequency.
f
VCO
V
co
=
REF
=
(C − 1)N
8f
is 100 MHz, n is 1, and m is 8, then f
Mf
VCO
1
REF
=
8Mf
N
REF
Altera Corporation
VCO
November 2007
is 800 MHz