EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 232

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III I/O Structure
Stratix III I/O
Structure
7–14
Stratix III Device Handbook, Volume 1
The I/O element (IOE) in Stratix III devices contains a bi-directional I/O
buffer and I/O registers to support a complete embedded bi-directional
single data rate or DDR transfer. The IOEs are located in I/O blocks
around the periphery of the Stratix III device. There are up to four IOEs
per row I/O block and four IOEs per column I/O block. The row IOEs
drive row, column, or direct link interconnects. The column IOEs drive
column interconnects.
The Stratix III bi-directional IOE also supports features such as:
■
■
■
■
■
■
■
■
■
■
■
■
Figure 7–8
The I/O registers are composed of the input path for handling data from
the pin to the core, the output path for handling data from the core to the
pin, and the output-enable (OE) path for handling the OE signal for the
output buffer. These registers allow faster source-synchronous
register-to-register transfers and resynchronization. The input path
consists of the DDR input registers, alignment and synchronization
registers, and HDR. You can bypass each block of the input path.
Programmable input delay
Programmable output-current strength
Programmable slew rate
Programmable output delay
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination with calibration
On-chip series termination without calibration
On-chip parallel termination with calibration
On-chip differential termination
PCI clamping diode
shows the Stratix III IOE structure.
Altera Corporation
November 2007