EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 93

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Clocking Modes
Altera Corporation
November 2007
f
FIFO Mode
All TriMatrix memory blocks support FIFO mode. MLABs are ideal for
designs with many small, shallow FIFO buffers. To implement FIFO
buffers in your design, use the Quartus II software FIFO MegaWizard.
Both single and dual-clock (asynchronous) FIFOs are supported.
Refer to the
more information on implementing FIFO buffers.
Stratix III TriMatrix memory blocks support the following clocking
modes:
■
■
■
■
1
Table 4–9
Independent Clock Mode
Stratix III TriMatrix memory blocks can implement independent clock
mode for true dual-port memories. In this mode, a separate clock is
available for each port (A and B). Clock A controls all registers on the
port A side, while clock B controls all registers on the port B side. Each
port also supports independent clock enables for port A and port B
registers. Asynchronous clears are supported only for output latches and
output registers on both ports.
Independent
Input/output
Read/write
Single clock
Table 4–9. Stratix III TriMatrix Memory Clock Modes
Clocking
Independent
Input/output
Read/write
Single clock
Mode
Violating the setup or hold time on the memory block address
registers could corrupt the memory contents. This applies to
both read and write operations.
shows the clocking mode versus memory mode support matrix.
Single- and Dual-Clock FIFO Megafunctions User Guide
Dual-Port
TriMatrix Embedded Memory Blocks in Stratix III Devices
Mode
True
v
v
—
v
Dual-Port
Simple
Mode
—
v
v
v
Stratix III Device Handbook, Volume 1
Single-Port
Mode
v
v
—
—
Mode
ROM
v
v
v
—
for
Mode
FIFO
4–19
v
v
—
—