EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 42

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Adaptive Logic Modules
2–8
Stratix III Device Handbook, Volume 1
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, and
synchronous load/clear inputs. Global signals, general-purpose I/O
pins, or any internal logic can drive the register's clock and clear control
signals. Either general-purpose I/O pins or internal logic can drive the
clock enable. For combinational functions, the register is bypassed and
the output of the LUT drives directly to the outputs of an ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers (refer to
ALM outputs can drive column, row, or direct link routing connections,
and one of these ALM outputs can also drive local interconnect resources.
This allows the LUT or adder to drive one output while the register drives
another output.
This feature, called register packing, improves device utilization because
the device can use the register and the combinational logic for unrelated
functions. Another special packing mode allows the register output to
feed back into the LUT of the same ALM so that the register is packed
with its own fan-out LUT. This provides another mechanism for
improved fitting. The ALM can also drive out registered and
unregistered versions of the LUT or adder output.
ALM Operating Modes
The Stratix III ALM can operate in one of the following modes:
■
■
■
■
■
Each mode uses ALM resources differently. In each mode, eleven
available inputs to an ALM—the eight data inputs from the LAB local
interconnect, carry-in from the previous ALM or LAB, the shared
arithmetic chain connection from the previous ALM or LAB, and the
register chain connection—are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, synchronous clear, synchronous load, and clock
enable control for the register. These LAB-wide signals are available in all
ALM modes.
1
Normal
Extended LUT Mode
Arithmetic
Shared Arithmetic
LUT-Register
Refer to
information on the LAB-wide control signals.
“LAB Control Signals” on page 2–4
Figure
2–6). For each set of output drivers, two
for more
Altera Corporation
October 2007