EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 322

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Differential Transmitter
Figure 9–3. Stratix III Transmitter in Clock Output Mode
Figure 9–4. Stratix III Serializer Bypass
9–6
Stratix III Device Handbook, Volume 1
Internal
Logic
Internal Logic
The Stratix III serializer can be bypassed to support DDR (×2) and SDR
(×1) operations to achieve a serialization factor of 2 and 1, respectively.
The I/O element (IOE) contains two data output registers that can each
operate in either DDR or SDR mode. The clock source for the registers in
the IOE can come from any routing resource, from the left/right PLL
(PLL_Lx/PLL_Rx), or from the top/bottom (PLL_Tx/PLL_Bx) PLL.
Figure 9–4
PLL_Lx /
PLL_Rx
Parallel
Transmitter Circuit
shows the serializer bypass path.
load_en
diffioclk
Serializer
IOE Supports SDR, DDR, or
Non-Registered Data Path
Series
IOE
Not used (connection exists)
Txclkout+
Txclkout–
Txclkout+
Txclkout–
Altera Corporation
November 2007