EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 660

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

I/O Timing
1–148
Stratix III Device Handbook, Volume 2
DIFFERENTIAL
1.8-V SSTL
CLASS I
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
Table 1–72. EP3SL110 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–73. EP3SL110 Column Pin Delay Adders for Regional Clock
I/O Standard
Parameter
Strength
Current
12mA
16mA
12mA
16mA
8mA
8mA
Table 1–73
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–73
Regional Clock.
Industrial
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock Parameter
PLL
PLL
PLL
PLL
PLL
PLL
—
—
Fast Model
and
specifies EP3SL110 Column Pin delay adders when using the
t
t
t
t
t
t
t
t
t
t
t
t
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
Commercial
Table 1–74
1.852
1.973
Industrial Commercial
—
—
—
—
—
—
—
—
—
—
—
—
show EP3SL110 regional clock (RCLK) adder
Fast Model
V
2.839
3.011
1.1V
CCL
-2
=
2.862
1.441
2.857
1.436
2.858
1.437
2.866
1.445
2.862
1.441
2.858
1.437
V
3.323
1.1V
3.12
CCL
-3
=
V
4.645 5.201 5.517 5.357 5.598
2.398 2.714 2.785 2.747 2.711
4.635 5.190 5.505 5.346 5.587
2.388 2.703 2.773 2.736 2.700
4.637 5.192 5.508 5.348 5.589
2.390 2.705 2.776 2.738 2.702
4.652 5.210 5.526 5.366 5.607
2.405 2.723 2.794 2.756 2.720
4.644 5.200 5.516 5.356 5.597
2.397 2.713 2.784 2.746 2.710
4.637 5.192 5.508 5.348 5.589
2.390 2.705 2.776 2.738 2.702
3.457
3.638
1.1V
V
1.1V
CCL
-2
CCL
-4
=
=
V
1.1V
V
3.297
3.462
CCL
1.1V
-3
CCL
Altera Corporation
=
=
-4L
November 2007
V
1.1V
CCL
3.251
3.452
-4
V
0.9V
CCL
=
=
V
1.1V
CCL
Units
ns
ns
=
-4L
V
0.9V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns