EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 173

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
Notes to
(1)
(2)
(3)
Clock input pins
External feedback input pin
Spread-spectrum input clock
tracking
PLL cascading
Compensation modes
PLL drives
VCO output drives DPA clock
Phase shift resolution
Programmable duty cycle
Output counter cascading
Input clock switchover
Table 6–11. Stratix III PLL Features (Part 2 of 2)
Provided input clock jitter is within input jitter tolerance specifications.
The dedicated path between adjacent PLLs is not available on L1, L4, R1, and R4 PLLs.
The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For
degree increments, the Stratix III device can shift all output frequencies in increments of at least 45 degrees.
Smaller degree increments are possible depending on the frequency and divide parameters.
Table
LVDSCLK
Feature
6–11:
and
LOADEN
8 single-ended or 4 differential pin
pairs
Single-ended or differential
Yes
Through GCLK and RCLK and
dedicated path between adjacent
PLLs
All except LVDS clock network
compensation
No
No
Down to 96.125 ps
Yes
Yes
Yes
Stratix III Top/Bottom PLLs
(1)
(3)
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
8 single-ended or 4 differential pin
pairs
Single-ended only
Yes
Through GCLK and RCLK and
dedicated path between adjacent
PLLs
All except external feedback mode
when using differential I/Os
Yes
Yes
Down to 96.125 ps
Yes
Yes
Yes
(1)
Stratix III Left/Right PLLs
(2)
(3)
6–23