EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 629

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EP3SE50F780I3N

Manufacturer Part Number
EP3SE50F780I3N
Description
Stratix III
Manufacturer
Altera
Datasheets

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Altera Corporation
November 2007
DIFFERENTIAL
1.8-V SSTL
CLASS I
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
1.8-V SSTL
CLASS II
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
RCLK input adder
RCLK PLL input adder
Table 1–62. EP3SL70 Row Pins Output Timing Parameters (Part 4 of 4)
Table 1–63. EP3SL70 Column Pin Delay Adders for Regional Clock
I/O Standard
Parameter
Strength
Current
12mA
16mA
12mA
16mA
8mA
8mA
Table 1–63
values that should be added to GCLK values. These adder values are
used to determine I/O timing when I/O pin is driven using regional
clock. This applies for all I/O standards supported by Stratix III devices.
Table 1–63
Regional Clock.
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Industrial
Clock Parameter
PLL
PLL
PLL
PLL
PLL
PLL
Fast Model
t
t
t
t
t
t
t
t
t
t
t
t
and
specifies EP3SL70 Column Pin delay adders when using the
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
CO
Stratix III Device Datasheet: DC and Switching Characteristics
Commercial
Table 1–64
1.872
1.9
Industrial Commercial
Fast Model
show EP3SL70 regional clock (RCLK) adder
V
2.875
2.851
1.1V
CCL
-2
2.662
1.513
2.657
1.508
2.658
1.509
2.666
1.517
2.662
1.513
2.658
1.509
=
Stratix III Device Handbook, Volume 2
V
3.159
3.134
1.1V
CCL
-3
=
4.331 4.862 5.160 5.008 5.159
2.489 2.808 2.891 2.847 2.828
4.321 4.851 5.148 4.997 5.148
2.479 2.797 2.879 2.836 2.817
4.323 4.853 5.151 4.999 5.150
2.481 2.799 2.882 2.838 2.819
4.338 4.871 5.169 5.017 5.168
2.496 2.817 2.900 2.856 2.837
4.330 4.861 5.159 5.007 5.158
2.488 2.807 2.890 2.846 2.827
4.323 4.853 5.151 4.999 5.150
2.481 2.799 2.882 2.838 2.819
V
1.1V
CCL
-2
3.458
3.449
V
1.1V
CCL
-4
=
=
V
1.1V
CCL
-3
3.298
3.289
V
1.1V
CCL
=
=
V
-4L
1.1V
CCL
-4
V
3.258
3.248
0.9V
=
CCL
=
V
1.1V
CCL
1–117
Units
=
-4L
ns
ns
V
0.9V
CCL
=
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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