EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 314

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
8–44
Stratix III Device Handbook, Volume 1
entire device. There are up to ten OCT calibration blocks to allow for
different types of terminations throughout the device. For more details,
refer to
1
The R
DQS/DQ groups where the R
planning to use dynamic calibrated OCT. The R
located in the first and the last ×4 DQS/DQ group on each side of the
device.
You should use the OCT R
and a dynamic OCT setting for bi-directional data signals.
Programmable IOE Delay Chains
The programmable delay chains in the Stratix III I/O registers can be
used as deskewing circuitry. Each pin can have a different input delay
from the pin to input register or a delay from the output register to the
output pin to ensure that the bus has the same delay going into or out of
the FPGA. This feature helps read and write time margins as it minimizes
the uncertainties between signals in the bus.
Programmable Output Buffer Delay
In addition to allowing for output buffer duty cycle adjustment, the
programmable output buffer delay chain allows you to adjust the delays
between data bits in your output bus to introduce or compensate
channel-to-channel skew. Incorporating skew to the output bus can help
minimize simultaneous switching events by enabling smaller parts of the
bus to switch simultaneously, instead of the whole bus. This feature is
also particularly useful in DDR3 SDRAM interfaces where the memory
system clock delay can be much larger than the data and data
clock/strobe delay. You can use this delay chain to add delay to the data
and data clock/strobe to better match the memory system clock delay.
Programmable Slew Rate Control
Stratix III devices provide four levels of static output slew rate control: 0,
1, 2, and 3, where 0 is the slowest slew rate setting and 3 is the fastest slew
rate setting. The default setting for the HSTL and SSTL I/O standards is 3.
A fast slew rate setting allows you to achieve higher I/O performance,
while a slow slew-rate setting reduces system noise and signal overshoot.
This feature is disabled if you are using the OCT Rs features.
UP
“Dynamic On-Chip Termination Control” on page
and R
You have the option to use the OCT R
calibration. However, the OCT R
calibration.
DN
pins can also be used as DQ pins, so you cannot use the
T/
R
S
UP
setting for uni-directional read/write data
and R
DN
T
pins are located if you are
feature is only available with
S
UP
feature with or without
and R
Altera Corporation
DN
November 2007
8–38.
pins are