EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 312

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Stratix III External Memory Interface Features
Figure 8–21. Stratix III IOE Output and Output-Enable Path Registers
Notes to
(1)
(2)
(3)
(4)
(5)
8–42
Stratix III Device Handbook, Volume 1
Half-Rate Clock (3)
From Core (2)
From Core (2)
From Core (2)
From Core (2)
From Core (2)
From Core (2)
Each register block of the output and output enable paths can be bypassed.
Data coming from the FPGA core are at half the frequency of the memory interface.
Half-rate and alignment clocks come from the PLL.
There are up to two levels of registers for data alignment. These registers are only used in DDR3 SDRAM interfaces.
The write clock can come from either the PLL or from the write leveling delay chain. The DQ write clock and DQS
write clock have a 90° offset between them.
Figure
Half Data Rate to Single Data Rate Output-Enable Registers
D
D
D
D
D
D
DFF
DFF
Half Data Rate to Single Data Rate Output Registers
DFF
DFF
DFF
DFF
8–21:
Q
Q
Q
Q
Q
Q
Alignment
Clock (3)
D
D
D
DFF
DFF
DFF
Q
Q
Q
0
1
0
1
0
1
Registers (4)
Registers (4)
Alignment
Alignment
Clock (5)
Write
Note (1)
DFF
DFF
Output Reg Bo
Double Data Rate Output-Enable Registers
Output Reg Ao
OE Reg B
OE Reg A
DFF
DFF
D
D
D
D
Double Data Rate Output Registers
Q
Q
Q
Q
OE
OE
1
0
1
0
OR2
Altera Corporation
November 2007
TRI
DQ or DQS