EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 39

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 2–4. LAB-Wide Control Signals
Adaptive Logic
Modules
Altera Corporation
October 2007
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
6
6
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrack
skew allows clock and control signal distribution in addition to data.
Figure 2–4
The basic building block of logic in the Stratix III architecture, the
adaptive logic module (ALM), provides advanced features with efficient
logic utilization. Each ALM contains a variety of look-up table
(LUT)-based resources that can be divided between two combinational
adaptive LUTs (ALUTs) and two registers. With up to eight inputs to the
two combinational ALUTs, one ALM can implement various
combinations of two functions. This adaptability allows an ALM to be
completely backward-compatible with four-input LUT architectures.
One ALM can also implement any function of up to six inputs and certain
seven-input functions.
6
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
labclk0
clock signals per LAB.
There are two unique
shows the LAB control signal generation circuit.
or asyncload
or labpreset
labclkena0
labclk1
labclkena1
Stratix III Device Handbook, Volume 1
labclk2
labclkena2
TM
interconnect's inherent low
syncload
labclr0
labclr1
synclr
2–5