EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 543

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
3.3-V LVTTL
3.3-V LVCMOS
3.0-V LVTTL
3.0-V LVCMOS
2.5v
1.8v
1.5v
1.2v
PCI
PCI-X
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
SSTL-15 CLASS I
SSTL-15 CLASS II
1.8v HSTL
CLASS I
Table 1–35. Output Timing Measurement methodology for Output Pins (Part 1 of 2)
I/O Standard
R
25
25
25
25
25
25
—
—
—
—
—
—
—
—
—
—
—
S
Figure 1–4. Output Register Clock to Output Timing Diagram
Notes to
(1)
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D
Figure
Output
Buffer
V
GND
CCIO
Stratix III Device Datasheet: DC and Switching Characteristics
1–4:
R
—
—
—
50
25
50
25
50
25
50
—
—
—
—
—
—
—
T
Output
Loading and Terminations
V
MEAS
V
2.375
1.425
2.325
2.325
1.375
1.375
2.85
2.85
2.85
2.85
1.71
1.14
2.85
2.85
1.66
1.66
1.66
C C I O
R
S
V
2.375
2.375
2.375
2.375
2.325
2.325
2.325
2.325
2.325
2.325
2.325
2.85
2.85
2.85
2.85
2.85
2.85
GND
V
C C P D
TT
Stratix III Device Handbook, Volume 2
R
C
T
L
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.05
1.02
1.02
1.02
1.02
1.02
1.02
1.02
V
C C
1.099
1.099
0.773
0.773
0.634
0.634
0.773
V
—
—
—
—
—
—
—
—
—
—
T T
Output
Output
p
n
C
L
10
10
R
(pF)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D
1–31
Measurement
V
M E A S
1.1875
0.7125
1.1625
1.1625
0.6875
0.6875
1.425
1.425
1.425
1.425
0.855
1.425
1.425
Point
0.57
0.83
0.83
0.83
(v)