EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 488

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Recovering From CRC Errors
Recovering
From CRC Errors
Conclusion
Referenced
Documents
Document
Revision History
15–14
Stratix III Device Handbook, Volume 1
October 2007
v1.2
May 2007 v1.1
November 2006
v1.0
Table 15–8. Document Revision History
Document
Date and
Version
●
●
●
●
Initial Release.
Minor edits to
Added new section
Added live links for references.
Minor edits to page 2, 3, 4, and 14. Updated
The system that the Stratix III device resides in must control the device
reconfiguration. After detecting an error on the CRC_ERROR pin, strobing
the nCONFIG signal low directs the system to perform the reconfiguration
at a time when it is safe for the system to reconfigure the device.
When the data bit is rewritten with the correct value by reconfiguring the
device, the device functions correctly.
While soft errors are uncommon in Altera devices, certain high-reliability
applications may require a design to account for these errors.
The purpose of the error detection CRC feature is to detect a flip in any of
the configuration CRAM bits in Stratix III devices due to a soft error. By
using the error detection circuitry, you can continuously verify the
integrity of the configuration CRAM bits.
1
This chapter references the following documents:
■
■
■
Table 15–8
AN 357: Error Detection Using CRC in Altera FPGA Devices
Robust SEU Mitigation with Stratix III FPGAs White Paper
TriMatrix Embedded Memory Blocks in Stratix III Devices
Table
For more information, refer to the
Stratix III FPGAs White
“Referenced
15–3.
shows the revision history for this document.
Changes Made
Documents”.
Paper.
Table
15–5.
Robust SEU Mitigation with
Summary of Changes
Altera Corporation
Minor edits.
Minor edits.
—
October 2007