EP3SE50F780I3N Altera, EP3SE50F780I3N Datasheet - Page 477

• Manufacturer Part Number: EP3SE50F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
October 2007
As soon as the device transitions into user mode, you can enable the error
detection process if you enable the CRC error detection option. The
internal 100 MHz configuration oscillator is divided down by a factor of
2 to 256 (at powers of 2) to be used as the clock source during the error
detection process. You set the clock divide factor in the option setting in
the Quartus II software.
A single 16-bit CRC calculation is done on a per-frame basis. Once it has
finished the CRC calculation for a frame, the resulting 16-bit signature is
hex 0000 if there are no detected CRAM bit errors in a frame by the
error detection circuitry and the output signal CRC_ERROR is 0. If a
CRAM bit error is detected by the circuitry within a frame in the device,
the resulting signature is non-zero. This causes the CRC engine to start
searching the error bit location.
The error detection in Stratix III devices calculates CRC check bits for each
frame and will pull the CRC_ERROR pin high when it detects bit errors in
the chip. Within a frame, it can detect all single-bit, double-bit, and
three-bit errors. The probability of more than three CRAM bits being
flipped by an SEU event is very low. In general, for all error patterns the
probability of detection is 99.998%.
The CRC engine reports the bit location and determines the type of error
for all single-bit errors and over 99.641% of double-adjacent errors. The
probability of other error patterns is very low and report of location of bit
flips is not guaranteed by the CRC engine.
You can also read-out the error bit location through the Joint Test Action
Group (JTAG) and the core interface. You would need to shift these bits
out through either the JTAG instruction, SHIFT_EDERROR_REG, or the
core interface before the CRC detects the next error in another frame. If
the next frame also has an error, you have to shift these bits out within the
amount of time of one frame CRC verification. You can choose to extend
this time interval by maximum 7-frame cycles, but this will slow down
the error recovery time for the SEU event. Refer to
minimum update interval for Stratix III devices. If these bits are not
shifted out before the next error location is found, the previous error
location and error message is overwritten by the new information. The
CRC circuit continues to run, and if an error is detected, you need to
decide whether to complete a reconfiguration or to ignore the CRC error.
The error detection logic continues to calculate the CRC_ERROR and 16-bit
signatures for the next frame of data regardless if any error has occurred
in the current frame or not. You need to monitor these signals and take
the appropriate actions if a soft error occurs.
Stratix III Device Handbook, Volume 1
SEU Mitigation in Stratix III Devices
Table 15–7
for the
15–3