LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 188

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 109. Pin multiplexing
P1_15 T12 x
P1_16 M7
P1_17 M8
P1_18 N12 x
P1_19 M11 x
P1_20 M10 x
P2_0
P2_1
P2_2
P2_3
P2_4
P2_5
P2_6
P2_7
P2_8
T16 x
N15 x
M15 x
J12
K11 x
K14 x
K16 x
H14 x
J16
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
62
64
66
67
68
70
75
81
84
87
88
91
95
96
98
Function level
0
GPIO0[2]
GPIO0[3]
GPIO0[12] U2_UCLK
GPIO0[13] U2_DIR
ENET_
TX_CLK
(ENET_R
EF_CLK)
GPIO0[15] SSP1_
R
R
R
R
R
R
R
GPIO0[7]
Boot pin
1
U2_TXD
U2_RXD
SSP1_SCK R
SSEL
U0_TXD
U0_RXD
U0_UCLK
I2C1_SDA
I2C1_SCL
CTIN_2
U0_DIR
CTOUT_1
CTOUT_0
2
R
R
R
R
R
EMC_A13
EMC_A12
EMC_A11
U3_TXD
U3_RXD
USB1_
VBUS
EMC_A10
U3_UCLK
U3_DIR
3
ENET_
RXD0
ENET_
CRS
ENET_
MDIO
ENET_
TXD0
R
ENET_
TXD1
USB0_
PWR_EN
USB0_
PWR_
FAULT
USB0_
IND1
CTIN_1
CTIN_0
ADCTRIG1 GPIO5[5]
USB0_
IND0
EMC_A9
EMC_A8
4
T0_MAT1
T0_MAT0
T0_CAP3
T0_MAT3
CLKOUT
T0_CAP2
GPIO5[0]
GPIO5[1]
GPIO5[2]
GPIO5[3]
GPIO5[4]
GPIO5[6]
R
GPIO5[7]
5
R
R
CAN1_TD R
CAN1_RD R
R
R
R
R
CTOUT_6 T3_CAP2
R
R
R
CTIN_7
R
R
6
R
R
I2S0_RX_
MCLK
R
T3_CAP0
T3_CAP1
T3_MAT0
T3_MAT1
T3_MAT2
T3_CAP3
T3_MAT3
R
R
R
USB0_
USB0_
R
R
R
7
R
ENET_
RX_DV
R
I2S1_TX_
SCK
R
ENET_
MDC
R
PWR_EN
PWR_
FAULT
USB0_
IND0
-
-
-
-
-
-
8
-
-
-
-
-
-
-
-
Reference
Table 111
Table 111
Table 112
Table 111
Table 111
Table 111
Table 111
Table 111
Table 111
Table 112
Table 112
Table 112
Table 111
Table 111
Table 111