LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 4
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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1.1 Introduction
1.2 Features
<Document ID>
User manual
The LPC18xx are ARM Cortex-M3 based microcontrollers for embedded applications.
The ARM Cortex-M3 is a next generation core that offers system enhancements such as
low power consumption, enhanced debug features, and a high level of support block
integration.
The LPC18xx operate at CPU frequencies of up to 150 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC18xx include up to 200 kB of on-chip SRAM data memory (flashless parts) or up
to 136 kB of on-chip SRAM and up to 1 MB of flash (parts with on-chip flash), a quad SPI
Flash Interface (SPIFI), a State Configurable Timer (SCT) subsystem, two High-speed
USB controllers, Ethernet, LCD, an external memory controller, and multiple digital and
analog peripherals.
Remark: This user manual describes the Rev ‘-’ and Rev ‘A’ versions of parts
LPC1850/30/20/10 (flashless parts) and provides a preliminary description of the
flash-based LPC18xx parts.
The following peripherals are available on LPC1350/30/20/10 Rev ‘A’ only:
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UM10430
Chapter 1: Introductory information
Rev. 00.13 — 20 July 2011
I2S1
C_CAN1
GPIO pin interrupts
GPIO group interrupt 0/1
Global Input Multiplexer Array (GIMA)
Processor core
– ARM Cortex-M3 processor, running at frequencies of up to 150 MHz.
– ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eight regions.
– ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
– Non-maskable Interrupt (NMI) input.
– JTAG and Serial Wire Debug, serial trace, eight breakpoints, and four watch points.
– ETM and ETB support.
– System tick timer.
On-chip memory (flashless parts LPC1850/30/20/10)
– Up to 200 kB SRAM total for code and data use.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
© NXP B.V. 2011. All rights reserved.
User manual
4 of 1164
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