LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 488

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
22.6.6 MAC MII Data register
22.6.7 MAC Flow control register
Table 408. CSR clock range values
The MII Data register stores Write data to be written to the PHY register located at the
address specified in the MAC_MII_ADDR register. This register also stores Read data
from the PHY register located at the address specified by the MAC_MII_ADDR register.
Table 409. MII Data register (MAC_MII_DATA, address 0x4001 0014) bit description
The Flow Control register controls the generation and reception of the Control (Pause
Command) frames by the MAC’s Flow control module. A Write to a register with the Busy
bit set to 1 triggers the Flow Control block to generate a Pause Control frame. The fields
of the control frame are selected as specified in the 802.3x specification, and the Pause
Time value from this register is used in the Pause Time field of the control frame. The
Busy bit remains set until the control frame is transferred onto the cable. The Host must
make sure that the Busy bit is cleared before writing to the register.
Bits 5:2
1101
1110
1111
Bit
15:0
31:16
Symbol
GD
-
All information provided in this document is subject to legal disclaimers.
Description
MII data
This contains the 16-bit data value read from the PHY after a
Management Read operation or the 16-bit data value to be
written to the PHY before a Management Write operation.
Reserved
Rev. 00.13 — 20 July 2011
clk_csr_i
-
-
-
Chapter 22: LPC18xx Ethernet
MDC clock
clk_csr_i/124
clk_csr_i/42
clk_csr_i/62
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
488 of 1164
Access
R/W
RO