LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 998

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Fig 154. PLL0 block diagram
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
CRYSTAL
32kHz
IDIVC
IDIVD
IDIVA
IDIVB
IDIVE
PLL1
IRC
PLL0_CTRL[27:24]
42.4.7.4.3 Use of PLL0 operating modes
CLKIN
PLL0 NPDIV[21:12]
The PLL contains three programmable dividers: pre-divider (N), feedback-divider (M) and
post-divider (P). The PLL contains a lock detector which measures the phase difference
between the rising edges of the input and feedback clocks. Only when this difference is
smaller than the so called “lock criterion” for more than seven consecutive input clock
periods, the lock output switches from low to high. A single too large phase difference
immediately resets the counter and causes the lock signal to drop (if it was high).
Requiring seven phase measurements in a row to be below a certain figure ensures that
the lock detector will not indicate lock until both the phase and frequency of the input and
feedback clocks are very well aligned. This effectively prevents false lock indications, and
thus ensures a glitch free lock signal.
To avoid frequency hang-up the PLL contains a frequency limiter. This feature is built in to
prevent the CCO from running too fast, this can occur if e.g. a wrong feedback-divider (M)
ratio is applied to the PLL.
Table 948. PLL operating modes
Normal Mode:
The pre- and post-divider can be selected to give:
N-DIVIDER
Mode
1: Normal
3: Power Down
•
•
•
•
mode 1a: Normal operating mode without post-divider and without pre-divider
mode 1b: Normal operating mode with post-divider and without pre-divider
mode 1c: Normal operating mode without post-divider and with pre-divider
mode 1d: Normal operating mode with post-divider and with pre-divider
“1”
PLL0_CTRL[2]
Direct Input
All information provided in this document is subject to legal disclaimers.
Mode 1 is the normal operating mode.
PLL0_Mode bit settings:
PD
0
1
Rev. 00.13 — 20 July 2011
PFD
Bandwidth Select P,I,R
PLL0_MDIV[31:17]
CLKEN
1
x
PLL0_MDIV[16:0]
M-DIVIDER
Filter
BYPASS
0
x
CCO
/2
PLL0_NPDIV[6:0]
P-DIVIDER
DIRECTI
1/0
x
PLL0_CTRL [3]
Direct Output
/2
Chapter 42: Appendix
PLL0_CTRL[4]
DIRECTO
1/0
x
CLKEN
PLL0_CTRL [1]
UM10430
Bypass
© NXP B.V. 2011. All rights reserved.
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019aac415
Q
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FRM
0
x
CLKOUT