LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 58

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Table 35.
Bit
3:2
5:4
7:6
9:8
11:10
13:12
15:14
Symbol
DMAMUXCH1
DMAMUXCH2
DMAMUXCH3
DMAMUXCH4
DMAMUXCH5
DMAMUXCH6
DMAMUXCH7
DMA muxing register (DMAMUX, address 0x4004 311C) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Description
Select DMA to peripheral connection for
DMA peripheral 1
Timer 0 match 0
USART0 transmit
Reserved
AES input
Select DMA to peripheral connection for
DMA peripheral 2.
Timer 0 match 1
USART0 receive
Reserved
AES output
Select DMA to peripheral connection for
DMA peripheral 3.
Timer 1 match 0
UART1 transmit
I2S1 channel 0
SSP1 transmit
Select DMA to peripheral connection for
DMA peripheral 4.
Timer 1 match 1
UART1 receive
I2S1 channel 1
SSP1 receive
Select DMA to peripheral connection for
DMA peripheral 5.
Timer 2 match 0
USART2 transmit
SSP1 transmit
Reserved
Selects DMA to peripheral connection for
DMA peripheral 6.
Timer 2 match 1
USART2 receive
SSP1 receive
Reserved
Selects DMA to peripheral connection for
DMA peripheral 7.
Timer 3 match l 0
USART3 transmit
SCT match output 0
Reserved
Chapter 7: LPC18xx Configuration Registers (CREG)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
…continued
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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