LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 483

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 403. MAC Configuration register (MAC_CONFIG, address 0x4001 0000) bit description
<Document ID>
User manual
Bit
12
13
14
15
16
19:17
20
21
Symbol
LM
DO
FES
PS
DCRS
IFG
JE
-
Description
Loopback Mode
When this bit is set, the MAC operates in loopback mode at MII. The (G)MII Receive
clock input is required for the loopback to work properly, as the Transmit clock is not
looped-back internally.
Disable Receive Own
When this bit is set, the MAC disables the reception of frames in Half-Duplex mode.
When this bit is reset, the MAC receives all packets that are given by the PHY while
transmitting.
This bit is not applicable if the MAC is operating in Full-Duplex mode.
Speed
Indicates the speed in Fast Ethernet (MII) mode:
0 = 10 Mbps
1 = 100 Mbps
Port select
1 = MII (100 Mbp) - this is the only allowed value.
Disable carrier sense during transmission
When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal
during frame transmission in Half-Duplex mode. This request results in no errors
generated due to Loss of Carrier or No Carrier during such transmission. When this
bit is low, the MAC transmitter generates such errors due to Carrier Sense and will
even abort the transmissions.
Inter-frame gap
These bits control the minimum IFG between frames during transmission.
000 = 96 bit times
001 = 88 bit times
010 = 80 bit times
...
000 = 40 bit times
Note that in Half-Duplex mode, the minimum IFG can be configured for 64 bit times
(IFG = 100) only. Lower values are not considered
Jumbo Frame Enable
When this bit is set, MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN
tagged frames) without reporting a giant frame error in the receive frame status.
Reserved.
.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
1
0
000
0
0
483 of 1164
Access
R/W
R/W
RO
R/W
R//W
R/W
RO