LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 354
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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20.1 How to read this chapter
20.2 Basic configuration
20.3 Features
<Document ID>
User manual
The USB0 Host/Device/OTG controller is available on parts LPC1850, LPC1830, and
LPC1820.
The USB0 Host/Device/OTG controller is configured as follows:
Table 294. USB0 clocking and power control
USB0 clock
USB0 register
interface clock
•
•
•
•
•
•
•
•
•
•
•
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UM10430
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Rev. 00.13 — 20 July 2011
See
The USB0 is reset by the USB0_RST (reset # 17).
The USB0 <tbd> is connected to interrupt slot # 8 in the NVIC, and the <tbd> is
connected to slot # 9 in the Event router.
Complies with Universal Serial Bus specification 2.0.
Complies with USB On-The-Go supplement.
Complies with Enhanced Host Controller Interface Specification.
Complies with AMBA specification.
Supports auto USB 2.0 mode discovery.
Supports all high-speed USB-compliant peripherals.
Supports all full-speed USB-compliant peripherals.
Supports all low-speed USB-compliant peripherals.
Supports software HNP and SRP for OTG peripherals.
Contains UTMI+ compliant transceiver (PHY).
Supports power management.
Supports six endpoints, control endpoint included.
Table 294
All information provided in this document is subject to legal disclaimers.
Base clock
BASE_USB0_CLK CLK_USB0
BASE_M3_CLK
for clocking and power control.
Rev. 00.13 — 20 July 2011
Branch clock
CLK_M3_USB0 150 MHz
Maximum
frequency
480 MHz
Notes
Uses PLL0 dedicated to
USB0. CLK_USB0 must be
480 MHz clock for the USB0
to operate in all three modes
(low-speed, full-speed, and
high-speed modes).
Uses PLL1.
© NXP B.V. 2011. All rights reserved.
User manual
354 of 1164
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