LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 369

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 310. USB Status register in host mode (USBSTS_H - address 0x4000 6144) register bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
11:9
Symbol Value
UI
UEI
PCI
FRI
-
AAI
-
SRI
-
-
20.6.4.2 Host mode
0
1
0
1
0
1
0
1
0
1
-
0
1
-
-
Description
USB interrupt (USBINT)
This bit is cleared by software writing a one to it.
This bit is set by the Host/Device Controller when the cause of an interrupt
is a completion of a USB transaction where the Transfer Descriptor (TD)
has an interrupt on complete (IOC) bit set.
This bit is also set by the Host/Device Controller when a short packet is
detected. A short packet is when the actual number of bytes received was
less than the expected number of bytes.
USB error interrupt (USBERRINT)
This bit is cleared by software writing a one to it.
When completion of a USB transaction results in an error condition, this bit
is set by the Host/Device Controller. This bit is set along with the USBINT
bit, if the TD on which the error interrupt occurred also had its interrupt on
complete (IOC) bit set.
Port change detect.
This bit is cleared by software writing a one to it.
The Host Controller sets this bit to a one when on any port a Connect
Status occurs, a Port Enable/Disable Change occurs, or the Force Port
Resume bit is set as the result of a J-K transition on the suspended port.
Frame list roll-over
This bit is cleared by software writing a one to it.
The Host Controller sets this bit to a one when the Frame List Index rolls
over from its maximum value to zero. The exact value at which the rollover
occurs depends on the frame list size. For example, if the frame list size (as
programmed in the Frame List Size field of the USBCMD register) is 1024,
the Frame Index Register rolls over every time FRINDEX bit 13 toggles.
Similarly, if the size is 512, the Host Controller sets this bit to a one every
time FRINDEX bit 12 toggles (see
Reserved.
Interrupt on async advance
This bit is cleared by software writing a one to it.
System software can force the host controller to issue an interrupt the next
time the host controller advances the asynchronous schedule by writing a
one to the Interrupt on Async Advance Doorbell bit in the USBCMD
register. This status bit indicates the assertion of that interrupt source.
Not used by the Host controller.
SOF received
This bit is cleared by software writing a one to it.
In host mode, this bit will be set every 125  s and can be used by host
controller driver as a time base.
Not used by the Host controller.
Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Section
20.6.6).
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
-
Access
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
R/WC
-
369 of 1164