LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 529
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Fig 51. Transmit descriptor fetch (read) for enhanced format
TDES3
TDES2
TDES0
TDES1
31
W
O
N
R
E
S
[30:26]
Ctrl
Table 437. Transmit descriptor word 0 (TDES0)
Bit
0
1
2
Buffer 2 Byte Count [28:16]
Buffer 2 Address [31:0] or Next Descriptor Address [31:0]
S
E
T
T
Symbol
DB
UF
ED
R
E
S
All information provided in this document is subject to legal disclaimers.
[23:20]
Ctrl
Description
Deferred Bit
When set, this bit indicates that the MAC defers before transmission
because of the presence of carrier. This bit is valid only in Half-Duplex mode.
Underflow Error
When set, this bit indicates that the MAC aborted the frame because data
arrived late from the Host memory. Underflow Error indicates that the DMA
encountered an empty transmit buffer while transmitting the frame. The
transmission process enters the Suspended state and sets both Transmit
Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]).
Excessive Deferral
When set, this bit indicates that the transmission has ended because of
excessive deferral of over 24,288 bit times (155,680 bits times in
1,000-Mbps mode or if Jumbo Frame is enabled) if the Deferral Check (DC)
bit in the MAC Control register is set high.
Rev. 00.13 — 20 July 2011
Buffer 1 Address [31:0]
R
E
S
Reserved for
Status [17:7]
R
E
S
Buffer 1 Byte Count [12:0]
Number
SLOT
[6:3]
Chapter 22: LPC18xx Ethernet
Reserved for
Status [3:0]
UM10430
© NXP B.V. 2011. All rights reserved.
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