LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 955

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
42.1.8.10 Interrupt Priority Register 4
42.1.8.12 Interrupt Priority Register 6
42.1.8.11 Interrupt Priority Register 5
The IPR4 register controls the priority of the fifth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 896. Interrupt Priority Register 4 (IPR4 - address 0xE000 E410) bit description
The IPR5 register controls the priority of the sixth group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 897. Interrupt Priority Register 5 (IPR5 - address 0xE000 E414) bit
The IPR6 register controls the priority of the seventh group of 4 peripheral interrupts. Each
interrupt can have one of 32 priorities, where 0 is the highest priority.
Table 898. Interrupt Priority Register 6 (IPR6 - address 0xE000 E418) bit description
Bit
2:0
7:3
10:8
15:11 IP_ADC0
18:16 -
23:19 IP_I2C0
26:24 -
31:27 IP_I2C1
Bit
2:0
7:3
10:8
15:11 IP_ADC1 ADC1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
18:16 -
23:19 IP_SSP0 SSP0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
26:24 -
31:27 IP_SSP1 SSP1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
Bit
2:0
7:3
10:8
Symbol
-
IP_MOTO
CONPWM
-
Symbol
-
-
-
Symbol
-
IP_USART0 USART0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
-
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved.These bits ignore writes, and read as 0.
Reserved.
Reserved.These bits ignore writes, and read as 0.
Reserved.These bits ignore writes, and read as 0.
Reserved.These bits ignore writes, and read as 0.
Description
Reserved.These bits ignore writes, and read as 0.
MOTOCONPWM interrupt priority. 0 = highest priority. 31 (0x1F) =
lowest priority.
Reserved.These bits ignore writes, and read as 0.
ADC0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest
priority.
Reserved.These bits ignore writes, and read as 0.
I2C0 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
Reserved.These bits ignore writes, and read as 0.
I2C1 interrupt priority. 0 = highest priority. 31 (0x1F) = lowest priority. 0
Description
Reserved.These bits ignore writes, and read as 0.
priority.
Reserved.These bits ignore writes, and read as 0.
Rev. 00.13 — 20 July 2011
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
955 of 1164
Reset
value
0
0
0
0
0
Reset
value
0
0
0
Reset
value
0
0
0
0
0
0