LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 880
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
37.10.3 Slave Receiver mode
In the slave receiver mode, a number of data bytes are received from a master transmitter
(see
follows:
Table 820. ADR usage in Slave Receiver mode
The upper 7 bits are the address to which the I
master. If the LSB (GC) is set, the I
(0x00); otherwise it ignores the General Call address.
Table 821. CONSET used to initialize Slave Receiver mode
The I
to logic 1 to enable the I
acknowledge its own slave address or the General Call address. STA, STO, and SI must
be reset.
When ADR and CON have been initialized, the I
own slave address followed by the data direction bit which must be “0” (W) for the I
block to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag (SI) is set and a valid status code can be read
from STAT. This status code is used to vector to a state service routine. The appropriate
action to be taken for each of these status codes is detailed in
receiver mode may also be entered if arbitration is lost while the I
mode (see status 0x68 and 0x78).
If the AA bit is reset during a transfer, the I
to SDA after the next received data byte. While AA is reset, the I
respond to its own slave address or a General Call address. However, the I
monitored and address recognition may be resumed at any time by setting AA. This
means that the AA bit may be used to temporarily isolate the I
Bit
Symbol
Bit
Symbol
Value
Figure
2
C-bus rate settings do not affect the I
7
7
-
-
142). To initiate the slave receiver mode, ADR and CON must be loaded as
All information provided in this document is subject to legal disclaimers.
6
6
I2EN
1
Rev. 00.13 — 20 July 2011
2
C block. The AA bit must be set to enable the I
5
5
STA
0
own slave 7-bit address
2
C block will respond to the General Call address
4
4
STO
0
2
C block will return a not acknowledge (logic 1)
2
C block in the slave mode. I2EN must be set
2
C block will respond when addressed by a
Chapter 37: LPC18xx I2C-bus interface
2
C block waits until it is addressed by its
3
3
SI
0
2
2
AA
1
2
Table
C block from the I
2
2
C block does not
C block is in the master
822. The slave
UM10430
-
1
1
-
© NXP B.V. 2011. All rights reserved.
2
C block to
2
C-bus is still
880 of 1164
0
GC
0
-
-
2
C-bus.
2
C
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