LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 967

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
42.2.6.6 Event enable register
Table 911. Event enable register (ENABLE - address 0x4004 4FE4) bit description
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Symbol
WAKEUP0_EN A 1 in this bit shows that the WAKEUP0 event has been
WAKEUP1_EN A 1 in this bit shows that the WAKEUP1 event has been
WAKEUP2_EN A 1 in this bit shows that the WAKEUP2 event has been
WAKEUP3_EN A 1 in this bit shows that the WAKEUP3 event has been
ATIMER_EN
RTC_EN
BOD_EN
WWDT_EN
ETH_EN
USB0_EN
USB1_EN
-
CAN_EN
TIM2_EN
TIM6_EN
QEI_EN
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the ATIMER event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the RTC event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the BOD event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the WWDT event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the ETHERNET event has been
enabled. This event wakes up the chip and contributes to the
event router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the USB0 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the USB1 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
Reserved.
A 1 in this bit shows that the CAN event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the TIM2 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the TIM6 event has been enabled.
This event wakes up the chip and contributes to the event
router interrupt when bit 0 = 1 in the STATUS register.
A 1 in this bit shows that the QEI event has been enabled. This
event wakes up the chip and contributes to the event router
interrupt when bit 0 = 1 in the STATUS register.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0
0
0
0
-
0
0
0
0