LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 95

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Fig 20. PLL1 block diagram
NSEL<1:0>
9.7.6.2 PLL1 description
9.7.6.3 Lock detector
9.7.6.4 Power-down control
/N
2
The block diagram of this PLL is shown in
to 25 MHz. The input clock is fed directly to the Phase-Frequency Detector (PFD). This
block compares the phase and frequency of its inputs, and generates a control signal
when phase and/ or frequency do not match. The loop filter filters these control signals
and drives the current controlled oscillator (CCO), which generates the main clock. The
CCO frequency range is 156 MHz to 320 MHz.These clocks are either divided by 2xP by
the programmable post divider to create the output clocks, or are sent directly to the
outputs. The main output clock is then divided by M by the programmable feedback
divider to generate the feedback clock. The output signal of the phase-frequency detector
is also monitored by the lock detector, to signal when the PLL has locked on to the input
clock.
The lock detector measures the phase difference between the rising edges of the input
and feedback clocks. Only when this difference is smaller than the so called “lock
criterion” for more than eight consecutive input clock periods, the lock output switches
from low to high. A single too large phase difference immediately resets the counter and
causes the lock signal to drop (if it was high). Requiring eight phase measurements in a
row to be below a certain figure ensures that the lock detector will not indicate lock until
both the phase and frequency of the input and feedback clocks are very well aligned. This
effectively prevents false lock indications, and thus ensures a glitch free lock signal.
To reduce the power consumption when the PLL clock is not needed, a Power-down
mode has been incorporated. In this mode, the internal current reference will be turned
off, the oscillator and the phase-frequency detector will be stopped and the dividers will
enter a reset state. While in Power-down mode, the lock output will be low to indicate that
PFD
analog section
DETECT
LOCK
MSEL<7:0>
/M
pd
cd
All information provided in this document is subject to legal disclaimers.
8
Rev. 00.13 — 20 July 2011
pd
LOCK
CCO
FBSEL
0
1
Chapter 9: LPC18xx Clock Generation Unit (CGU)
Figure
BYPASS
0
1
20. The input frequency range is 10 MHz
PSEL<1:0>
2
/2P
pd
cd
UM10430
DIRECT
© NXP B.V. 2011. All rights reserved.
0
1
FCLKOUT
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