LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 319
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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18.6.34 Internal DMAC Status Register (IDSTS)
Table 258. Internal DMAC Status Register (IDSTS, address 0x4000 408C) bit description
Bit
0
1
2
3
4
5
7:6
8
9
12:10 EB
16:13 FSM
31:16 -
Symbol Description
TI
RI
FBE
-
DU
CES
-
NIS
AIS
All information provided in this document is subject to legal disclaimers.
Transmit Interrupt. Indicates that data transmission is finished for a
descriptor. Writing a 1 clears this bit.
Receive Interrupt. Indicates the completion of data reception for a
descriptor. Writing a 1 clears this bit.
Fatal Bus Error Interrupt. Indicates that a Bus Error occurred
(IDSTS[12:10]). When this bit is set, the DMA disables all its bus
accesses. Writing a 1 clears this bit.
Reserved
Descriptor Unavailable Interrupt. This bit is set when the descriptor
is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears
this bit.
Card Error Summary. Indicates the status of the transaction to/from
the card; also present in RINTSTS. Indicates the logical OR of the
following bits: EBE - End Bit Error RTO - Response Time-out/Boot
Ack Time-out RCRC - Response CRC SBE - Start Bit Error DRTO -
Data Read Time-out/BDS time-out DCRC - Data CRC for Receive
RE - Response Error Writing a 1 clears this bit.
Reserved
Normal Interrupt Summary. Logical OR of the following: IDSTS[0] -
Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits
affect this bit. This is a sticky bit and must be cleared each time a
corresponding bit that causes NIS to be set is cleared. Writing a 1
clears this bit.
Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2]
- Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card
Error Summary Interrupt Only unmasked bits affect this bit. This is a
sticky bit and must be cleared each time a corresponding bit that
causes AIS to be set is cleared. Writing a 1 clears this bit.
Error Bits. Indicates the type of error that caused a Bus Error. Valid
only with Fatal Bus Error bit (IDSTS[2]) set. This field does not
generate an interrupt. 001 - Host Abort received during transmission
010 - Host Abort received during reception Others: Reserved EB is
read-only.
DMAC FSM present state.
0 - DMA_IDLE
1 - DMA_SUSPEND
2 - DESC_RD
3 - DESC_CHK
4 - DMA_RD_REQ_WAIT
5 - DMA_WR_REQ_WAIT
6 - DMA_RD
7 - DMA_WR
8 - DESC_CLOSE
This bit is read-only.
Reserved
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
0
0
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