LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 46

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Table 21.
Bit
7
8
9
10
11
12
13
14
Symbol
WWDT_E
ETH_E
USB0_E
USB1_E
-
CAN_E
TIM2_E
TIM6_E
Edge configuration register (EDGE - address 0x4004 4004) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
-
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Edge/level detect mode for WWDTD event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 7 in the HILO
register is 0. Detect rising edge if bit 7 in the HILO
register is 1.
Level detect.
Edge detect. Detect falling edge if bit 8 in the HILO
register is 0. Detect rising edge if bit 8 in the HILO
register is 1.
Level detect.
Edge detect. Detect falling edge if bit 9 in the HILO
register is 0. Detect rising edge if bit 9 in the HILO
register is 1.
Level detect.
Edge detect. Detect falling edge if bit 10 in the HILO
register is 0. Detect rising edge if bit 10 in the HILO
register is 1.
Reserved.
Edge/level detect mode for C_CAN event. The
corresponding bit in the EDGE register must be 0.
Level detect.
Edge detect. Detect falling edge if bit 12 in the HILO
register is 0. Detect rising edge if bit 12 in the HILO
register is 1.
Edge/level detect mode for combined timer output 2
event. The corresponding bit in the EDGE register must
be 0.
Level detect.
Edge detect. Detect falling edge if bit 13 in the HILO
register is 0. Detect rising edge if bit 13 in the HILO
register is 1.
Edge/level detect mode for combined timer output 6
event. The corresponding bit in the EDGE register must
be 0.
Level detect.
Edge detect. Detect falling edge if bit 14 in the HILO
register is 0. Detect rising edge if bit 14 in the HILO
register is 1.
The corresponding bit in the EDGE register must be 0.
The corresponding bit in the EDGE register must be 0.
The corresponding bit in the EDGE register must be 0.
Chapter 6: LPC18xx Event router
UM10430
© NXP B.V. 2011. All rights reserved.
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0
0
0
Reset
value
0
0
0
0