LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 513

• Manufacturer Part Number: LPC1810FET100,551
• Description: IC MCU 32BIT 136KB FLSH 100TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1810FET100,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Size: -
• Program Memory Type: ROMless
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
22.7.2 DMA arbiter functions
Remark:
If you have enabled the transmit (Tx) DMA and receive (Rx) DMA of a channel, you can
specify which DMA gets the bus when the channel gets the control of the bus. You can set
the priority between the corresponding Tx DMA and Rx DMA by using the bit 27 (TXPR:
Transmit Priority) of the DMA Bus Mode Register). For round-robin arbitration, you can
use the bits [15:14] (PR: Priority Ratio) of the Bus Mode Register to specify the weighted
priority between the Tx DMA and Rx DMA.
priority scheme between Tx DMA and Rx DMA.
Table 436. Priority scheme for transmit and receive DMA
Bit 27
0
0
0
0
0
1
1
1
1
1
2. Disable the MAC transmitter and MAC receiver by clearing the appropriate bits in the
3. Wait until the Receive DMA empties all the frames from the Rx FIFO (a software timer
4. Enable Power-Down mode by appropriately configuring the PMT registers.
5. Enable the MAC Receiver and enter Power-Down mode.
6. Gate the application and transmit clock inputs to the core (and other relevant clocks in
7. On receiving a valid wake-up frame, the MAC PMT interrupt signal and exits
8. On receiving the interrupt, the system must enable the application and transmit clock
9. Read the PMT Status register to clear the interrupt, then enable the other modules in
MAC Configuration register.
may be required).
the system) to reduce power and enter Sleep mode.
Power-Down mode.
inputs to the core.
the system and resume normal operation.
Bit 15
x
0
0
1
1
x
0
0
1
1
All information provided in this document is subject to legal disclaimers.
Bit 14
x
0
1
0
1
x
0
1
0
1
Rev. 00.13 — 20 July 2011
Bit 1
x
0
0
0
0
1
0
0
0
0
Priority scheme
Rx always has priority over Tx
simultaneous requests.
Rx has priority over Tx in the ratio 2:1.
Rx has priority over Tx in the ratio 3:1.
Rx has priority over Tx in the ratio 4:1.
Tx always has priority over Rx.
Tx and Rx have equal priority. Tx gets the access first on
simultaneous requests.
Tx has priority over Rx in the ratio 2:1.
Tx has priority over Rx in the ratio 3:1.
Tx has priority over Rx in the ratio 4:1.
Tx and Rx have equal priority. Rx gets the access first on
Table 436
provides information about the
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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