LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 970
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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42.3 LPC1850/30/20/10 Rev ‘-’ CREG
<Document ID>
User manual
42.3.1 How to read this chapter
42.3.2 Basic configuration
42.3.3 Features
Table 913. Interrupt set status register (SET_STAT - address 0x4004 4FEC) bit description
Remark: This chapter applies to LPC1850/30/20/10 Rev ‘-’ only.
The available peripherals vary for different parts.
If a peripheral is not available, the corresponding bits in the CREG registers are reserved.
The CREG block is configured as follows:
Table 914. CREG clocking and power control
The following settings are controlled in the configuration register block:
In addition, the Creg block contains the part id and the part configuration information.
Bit
18:17
19
31:20
CREG
•
•
•
•
•
•
•
•
•
•
•
•
Ethernet: available on LPC1850/30.
USB0: available on LPC1850/30/20.
USB1: available on LPC1850/30.
See
The CREG block can not be reset by software.
BOD trip settings
Oscillator output
DMA-to-peripheral muxing
Ethernet mode
Memory mapping
Timer/UART inputs
USB0 ATX
Symbol
-
RESET_SETST
-
Table 925
Base clock
BASE_M3_CLK
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Description
Reserved.
Writing a 1 to this bit sets the STATUS event bit 19 in the
STATUS register.
Reserved.
CLK_M3_CREG
Branch clock
Chapter 42: Appendix
Maximum frequency
150 MHz
UM10430
© NXP B.V. 2011. All rights reserved.
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