LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 938
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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42.1 LPC1850/30/20/10 Rev ‘-’ NVIC
<Document ID>
User manual
42.1.1 How to read this chapter
42.1.2 Basic configuration
42.1.3 Features
42.1.4 General description
42.1.5 Pin description
Remark: This chapter describes the NVIC connections of parts LPC1850/30/20/10
Rev “-”.
The available NVIC interrupt sources vary for different parts.
The NVIC is part of the ARM Cortex-M3 core.
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M3. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
Refer to the Cortex-M3 User Guide for details of NVIC operation.
Table 884. NVIC pin description
Function
NMI
•
•
•
•
•
•
•
•
•
•
•
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UM10430
Chapter 42: Appendix
Rev. 00.13 — 20 July 2011
Ethernet interrupt: available on LPC1850/30.
USB0 interrupt: available on LPC1850/30/20.
USB1 interrupt: available on LPC1850/30.
SDIO interrupt: not available.
Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M3
Tightly coupled interrupt controller provides low interrupt latency
Controls system exceptions and peripheral interrupts
On the LPC18xx, the NVIC supports 32 vectored interrupts
32 programmable interrupt priority levels, with hardware priority level masking
Relocatable vector table
Non-Maskable Interrupt
Software interrupt generation
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Direction
I
Description
External Non-Maskable Interrupt (NMI) input
© NXP B.V. 2011. All rights reserved.
User manual
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