LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 619
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 529. SCT configuration example
<Document ID>
User manual
Configuration
Counter
Clock base
Match/Capture registers
Define match values
Define match reload
values
Define when event 0
occurs
Define when event 1
occurs
Define when event 2
occurs
Define when event 3
occurs
Define how event 3
changes the state
output 0
counter
Fig 69. SCT configuration example
input 0
SCT
SCT
match
events
SC
EV0
EV1
EV2
STATE 0
EV0
This application of the SCT uses the following configuration (all register values not listed
in
CONFIG
REGMODE
Register(s)
CONFIG
CTRL
MATCH0/1/2/4/5
MATCHREL0/1/2/4/5
EVCTRL0
EVCTRL1
EVCTRL2
EVCTRL3
EVCTRL3
Table 529
input transition
EV1
events
EV3
are set to their default values):
EV2
All information provided in this document is subject to legal disclaimers.
EV4
Rev. 00.13 — 20 July 2011
EV5
Setting
Uses one counter (UNIFY = 1).
Uses unidirectional counter (BIDIR_L = 0).
Uses default values for clock configuration.
Configure one match register for each match event by setting
REGMODE_L bits 0,1, 2, 4, 5 to 0. This is the default.
Set a match value MATCH0/1/2/4/5_L in each register.
Set a match reload value RELOAD0/1/2/4/5_L in each register
(same as the match value in this example).
Set STATEV bits to 1 and the STATED bit to 1. Event 3 changes the
state to state 1.
•
•
•
•
•
•
•
•
•
Set COMBMODE = 0x1. Event 0 uses match condition only.
Set MATCHSEL = 0. Select match value of match register 0.
Set COMBMODE = 0x1. Event 1 uses match condition only.
Set MATCHSEL = 1. Select match value of match register 1.
Set COMBMODE = 0x1. Event 2 uses match condition only.
Set MATCHSEL = 2. Select match value of match register 2.
Set COMBMODE = 0x2. Event 3 uses I/O condition only.
Set IOSEL = 0. Select input 0.
Set IOCOND = 0x2. Input 0 goes LOW.
EV2
STATE 1
Chapter 24: LPC18xx State Configurable Timer (SCT)
EV4
EV5
EV6
EV2
EV0
EV1
EV2
STATE 0
EV0
UM10430
© NXP B.V. 2011. All rights reserved.
EV1
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EV2
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